a billion ops/sec!.. you are da man!! {{sigh}} ..if i had only one-tenth your manliness i'd rue the markets
if your NIC is on the PCI bus, you may be asking for trouble since all devices on that bus share interrupts. wee
No! The new (Quad only?) opteron boards have dual channel PCI/X buses! That is the whole point! Check out: http://www.amdboard.com/tyan_s4882_opteron_board.html Look at "Expansion Slots" - "Two independent PCI-X buses." However, I do not know how the hardware interacts with the OS on this. To add to that, I have no idea on what bus the _onboard_ NICs are. Even in this case, there is probably no way to assure that the NIC's get one PCI-X bus to itself. Ugh, I honestly don't know. nitro
The win32 kernel (including tcp/ip) already runs at a priority between "high" and "realtime". User process running at "high" priority can not preempt the kernel. User process at "realtime" will preempt the kernel causing the system to freeze.
i think it's a driver-level concern -- try it for sure -- you may get good results by exploiting the cache on the one cpu. be sure to benchmark it though with affinity off and on. if it's not better on, then bag it. recognize, however, that the ideal solution is to use software designed to exploit multi-processor machines, i.e, with lots of parallelism, and not simply to "lean" on one processor. good luck.
You should be able to profile your code and figure out roughly how much cache is optimal. You can also modify the core algorithm, adjust it's memory footprint then examine how performance is affected.
prophet, Can you provide me with a link that shows that the TCP/IP stack is already running at these priorities? nitro
The first part makes sense. However, I don't follow the second. The memory footprint of the program has nothing to do with the cache hit on the CPUs internal cache(s)? My machine has gobs of RAM (4GB at this point.) It is my Xeon CPUs that only have 512KB of CACHE, as opposed to the 3MB cache some of these MP CPU's have. As it is, I have heard that too much cache can slow down a program, as the pipeline gets flushed (I believe that AMD and INTC processors have a similar strategy for cache hits/misses.) if no cache hit and that takes some time. I really need to understand the way that the caches interact. nitro
BTW, I found this link, but I do not believe it has the info I am looking for: http://www.microsoft.com/windows200...munications/networkbasics/tcpip_implement.asp nitro